1. Field of the Invention
The present invention relates generally to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device, which can prevent impurities from entering into a substrate through Peroxy Linkage Defects (hereinafter referred to as ‘PLD’) existing within an oxide film when an oxide/nitride film double spacer is applied to the manufacture of a transistor.
2. Description of the Prior Art
As a semiconductor device becomes highly integrated, design rules for a gate electrode or a source/drain region and contacts therewith of a Metal Oxide Semiconductor Field Effect Transistor (hereinafter referred to as ‘MOSFET’) are orienting toward size reduction over the whole processes in order to diminish a size of the device. However, since a width of the gate electrode is proportional to electric resistance, reducing the width by a factor of N brings about increase of the electric resistance by N times, which results in a problem of a loss in operating speed of the semiconductor device.
Thereupon, taking advantage of characteristics of a polysilicon layer/oxide film interface which exhibits the most stable MOSFET characteristics, polycide having a laminated structure of a polysilicon layer and a silicide film may be used as a low-resistance gate for reducing resistance of the gate electrode.
Also, a pn junction is formed by ion-implanting n- or p-type impurities into a p- or n-type substrate and then performing heat treatment to activate the impurities and form a diffusion region. However, in a case of a semiconductor device with a reduced channel width, a short channel effect may arise due to lateral diffusion from the diffusion region. Thus, there are employed various methods for preventing this effect, including a method in which the junction with a shallow depth is formed, a source/drain region is formed in a Lightly Doped Drain (hereinafter referred to as ‘LDD’) structure having a lowly-concentrated impurity region so as to prevent junction failure due to field concentration on a drain and prevent threshold voltage fluctuation effected by thermal charges, and halo ion implantation is performed by an inclined ion implantation technique.
FIG. 1 is a sectional view of a semiconductor device according to the prior art, which shows an example of a double gate electrode and a double spacer.
First of all, a gate oxide film 12 is formed on a semiconductor substrate 10 and then a first gate conductive layer 14, a second gate conductive layer 16 and a hard mask layer 18 are successively deposited on the gate oxide film 10. Thereafter, the layers 14, 16, 18 are patterned using a gate mask to form a gate electrode consisting of first and second gate conductive layer patterns 14, 16 and a hard mask layer pattern 18 laminated thereon.
Next, a spacer oxide film and a spacer nitride film are successively coated over the entire surface of the resultant structure and are etched back to form a first and a second spacer 20, 22 on sidewalls of the first and second gate conductive layer patterns 14, 16 and the hard mask layer pattern 18. Here, the reason why the spacer is formed in a double structure is that, when the spacer is formed of only the nitride film, stresses are incurred in the silicon substrate and so characteristics of the device are deteriorated.
In the above-mentioned method for manufacturing a semiconductor device, the double spacer consisting of the oxide and nitride films may prevent the nitride film from incurring stresses in the semiconductor substrate because the oxide film comes in contact with the substrate. However, impurities such as hydrogen, etc. coming from an insulating interlayer over the gate electrode enter the oxide film through PLDs existing therein and may be diffused up to into the semiconductor substrate, which causes a gate hump phenomenon where the diffused impurities deactivates n- or p-type impurities doped in a channel region and thus a threshold voltage (Vt) of the device varies. This tendency becoming more deepened with the downsizing of the device raises a problem of lowering in process yield and operating characteristics of the device.